Microchip Technology /ATSAME51J19A /CMCC /TYPE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TYPE

WAYNUM=DMAPPED, CLSIZE=CLSIZE_4B, CSIZE=CSIZE_1KB

Description

Cache Type Register

Fields

GCLK	dynamic Clock Gating supported
RRP	Round Robin Policy supported
WAYNUM	Number of Way 0 (DMAPPED): Direct Mapped Cache 1 (ARCH2WAY): 2-WAY set associative 2 (ARCH4WAY): 4-WAY set associative
LCKDOWN	Lock Down supported
CSIZE	Cache Size 0 (CSIZE_1KB): Cache Size is 1 KB 1 (CSIZE_2KB): Cache Size is 2 KB 2 (CSIZE_4KB): Cache Size is 4 KB 3 (CSIZE_8KB): Cache Size is 8 KB 4 (CSIZE_16KB): Cache Size is 16 KB 5 (CSIZE_32KB): Cache Size is 32 KB 6 (CSIZE_64KB): Cache Size is 64 KB
CLSIZE	Cache Line Size 0 (CLSIZE_4B): Cache Line Size is 4 bytes 1 (CLSIZE_8B): Cache Line Size is 8 bytes 2 (CLSIZE_16B): Cache Line Size is 16 bytes 3 (CLSIZE_32B): Cache Line Size is 32 bytes 4 (CLSIZE_64B): Cache Line Size is 64 bytes 5 (CLSIZE_128B): Cache Line Size is 128 bytes

Links

()